Modern radio transceivers, which are made up of dedicated hardware for, e.g., synthesizing, modulating or demodulating, characterizing, encoding or decoding, filtering, mixing and converting signals, are typically controlled in real-time by a processor. However, the processor controls the transceiver hardware only to a limited degree. The processor is initially responsible for loading sets of parameters (e.g., thresholds, constants, coefficients, etc., that establish various quantities, levels, maxima, minima, ranges, rates, rates of change, etc.) into various registers associated with the transceiver hardware to establish its operating characteristics. Once the transceiver hardware has been configured, the processor is thereafter responsible for queuing data that the transceiver is to transmit and further processing data that the receiver has received (e.g., assembling and error-checking packets of data, prompting the retransmission of data that had been previously been corrupted and indicating the receipt of data to downstream elements of a larger system). The transceiver hardware itself is responsible for transmitting and receiving the signals bearing the data; the processor may be properly regarded as ancillary to the transceiver hardware.
This general architecture is prevalent among conventional processor-controlled transceivers and has proven successful in a wide array of applications. However, it is always desirable to enhance the operation of a transceiver. More specifically, it is often desirable to make the transceiver more flexible in terms of the conditions under which it is able to operate. What is needed is a better way to control a transceiver with a processor, particularly when the transceiver hardware is operating aberrantly.